26.2 Timer2 Output

The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time the T2TMR value matches the T2PR value. This signal can also be selected as an input to other Core Independent Peripherals.

In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See the “PWM Overview” and “PWM Period” sections in the “CCP - Capture/Compare/PWM Module” chapter for more details on setting up Timer2 for use with the CCP and PWM modules.