20.12.20 Component Identification 1
| Name: | CID1 |
| Offset: | 0x1FF4 |
| Reset: | 0x00000010 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCLASS[3:0] | PREAMBLE[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |
Bits 7:4 – CCLASS[3:0] Component Class
These bits will always return 0x1 when read indicating that this Arm CoreSight component is ROM table (refer to the Arm Debug Interface v5 Architecture Specification at http://www.arm.com).
Bits 3:0 – PREAMBLE[3:0] Preamble
These bits will always return 0x00 when read.