26.6.2 Control B

Name: CTRLB
Offset: 0x04
Reset: 0x00000080
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     CACHEDIS[1:0]READMODE[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
       SLEEPPRM[1:0] 
Access R/WR/W 
Reset 00 
Bit 76543210 
 MANW  RWS[3:0]  
Access R/WR/WR/WR/WR/W 
Reset 10000 

Bits 19:18 – CACHEDIS[1:0] Cache Disable

This bit is used to disable the cache.

ValueDescription
0x3 The Data Flash cache is enabled, the main array cache is disabled
0x2 The Data Flash cache is enabled, the main array cache is enabled
0x1 The Data Flash cache is disabled, the main array cache is disabled
0x0 The Data Flash cache is disabled, the main array cache is enabled

Bits 17:16 – READMODE[1:0] NVMCTRL Read Mode

ValueNameDescription
0x0 NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
0x1 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increased run time.
0x2 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed Flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
0x3 Reserved

Bits 9:8 – SLEEPPRM[1:0] Power Reduction Mode during Sleep

Indicates the Power Reduction Mode during sleep.
ValueNameDescription
0x0 WAKEONACCESS NVM block enters low-power mode when entering sleep.
 NVM block exits low-power mode upon first access.
0x1 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.
 NVM block exits low-power mode when exiting sleep.
0x2 Reserved
0x3 DISABLED Auto power reduction disabled.

Bit 7 – MANW Manual Write

Note that reset value of this bit is '1'.

ValueDescription
0 Writing to the last word in the page buffer will initiate a write operation to the page addressed by the last write operation. This includes writes to memory and auxiliary rows.
1 Write commands must be issued through the CTRLA.CMD register.

Bits 4:1 – RWS[3:0] NVM Read Wait States

These bits control the number of wait states for a read operation. '0' indicates zero wait states, '1' indicates one wait state, etc., up to 15 wait states.

This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency. Refer to NVM Max Speed Characteristics in the 43 Electrical Characteristics 85℃ chapter.