40.6.16 Debug Control
| Name: | DBGCTRL |
| Offset: | 0x24 |
| Reset: | 0x00 |
| Property: | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DBGRUN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – DBGRUN Debug Run
This bit is reset by a system software reset.
This bits controls the functionality when the CPU is halted by an external debugger.
| Value | Description |
|---|---|
| 0 | The TSENS is halted when the CPU is halted by an external debugger. Any on-going measurement will complete. |
| 1 | The TSENS continues normal operation when the CPU is halted by an external debugger. |