15.7.9 32.768 kHz Internal Oscillator (OSC32K) Control

Name: OSC32K
Offset: 0x18
Reset: 0x003F 0080 (Writing action by User required)
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  CALIB[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0111111 
Bit 15141312111098 
    WRTLOCK STARTUP[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 ONDEMANDRUNSTDBY  EN1KEN32KENABLE  
Access R/WR/WR/WR/WR/W 
Reset 10000 

Bits 22:16 – CALIB[6:0] Oscillator Calibration

These bits control the oscillator calibration. The calibration values must be loaded by the user from the NVM Software Calibration Area.

Bit 12 – WRTLOCK Write Lock

This bit locks the OSC32K register for future writes, effectively freezing the OSC32K configuration.

ValueDescription
0 The OSC32K configuration is not locked.
1 The OSC32K configuration is locked.

Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time

These bits select start-up time for the oscillator.

The OSCULP32K oscillator is used as input clock to the start-up counter.

Table 15-4. Start-Up Time for 32.768 kHz Internal Oscillator
STARTUP[2:0] Number of OSC32K clock cycles
0x0 3
0x1 4
0x2 6
0x3 10
0x4 18
0x5 34
0x6 66
0x7 130

Bit 7 – ONDEMAND On Demand Control

This bit controls how the OSC32K behaves when a peripheral clock request is detected. For details, refer to OSC32K Sleep Behavior.

Bit 6 – RUNSTDBY Run in Standby

This bit controls how the OSC32K behaves during standby sleep mode. For details, refer to OSC32K Sleep Behavior.

Bit 3 – EN1K 1.024 kHz Output Enable

ValueDescription
0 The 1.024 kHz output is disabled.
1 The 1.024 kHz output is enabled, and available internally only for RTC.

Bit 2 – EN32K 32.768 kHz Output Enable

ValueDescription
0 The 32.768 kHz output is disabled.
1 The 32.768 kHz output is enabled, and can be routed to GCLK/GCLK_IO.

Bit 1 – ENABLE Oscillator Enable

ValueDescription
0 The oscillator is disabled.
1 The oscillator is enabled.