19.6.1 Write Control

Name:	WRCTRL
Offset:	0x00
Reset:	0x00000000
Property:	–


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	KEY[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PERID[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PERID[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bits 23:16 – KEY[7:0] Peripheral Access Control Key

These bits define the peripheral access control key:

Value	Name	Description
0x0	OFF	No action
0x1	CLEAR	Clear the peripheral write control
0x2	SET	Set the peripheral write control
0x3	LOCK	Set and lock the peripheral write control until the next hardware reset

Bits 15:0 – PERID[15:0] Peripheral Identifier

The PERID represents the peripheral whose control is changed using the WRCTRL.KEY.

Table 19-1. Peripheral Identifier
Peripheral	Identifier
APBA Peripherals
PAC	0
PM	1
MCLK	2
RSTC	3
OSCCTRL	4
OSC32KCTRL	5
SUPC	6
GCLK	7
WDT	8
RTC	9
EIC	10
FREQM ⁽⁴⁾	11
TEMPS ⁽¹⁾	12
APBB Peripherals
PORT ^(2,3)	32
DSU	33
NVMCTRL	34
DMAC	35
MTB	36
HMATRIXHS	37
APBC Peripherals
EVSYS	64
SERCOM0	65
SERCOM1	66
SERCOM2	67
SERCOM3	68
TCC0	73
TCC1	74
TCC2	75
TC0	76
TC1	77
TC2	78
TC3	79
TC4	80
ADC0	81
ADC1	82
SDADC	83
AC	84
DAC	85
CCL	87
PDEC	90

Note:

PAC protection for the TSENS should only be used when the TSENS is in Free Run mode.
IOBUS writes are not prevented to PAC write-protected registers when the PORT module is PAC protected.
PORT read/write attempts on non-implemented registers, including addresses beyond the last implemented register group do not generate a PAC protection error.
Reading the Frequency Meter Control B register (FREQM.CTRLB) will result in a PAC error.

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