26.5.2 Memory Organization

Refer to the Physical Memory Map for memory sizes and addresses for each device.

The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row Organization figure. One page is made of 64 bytes, that is sixteen 32bits words, or height 64bits double words. One row is made of 4 pages, that is 256 bytes, or sixty four 32bits words, or sixteen 64bits double words. The NVM has a row-erase granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the row, while four write operations are used to write the complete row.

The NVM block contains a calibration and auxiliary space, a Data Flash section, and a main array that is memory mapped. Refer to the NVM Organization figure below for details.

The calibration and auxiliary space contains factory calibration and system configuration information. These spaces can be read from the AHB bus in the same way as the main NVM main address space.

In addition, the lower rows in the NVM main address space can be allocated as a boot loader section. Its size is configured thanks to the BOOTPROT fuses (refer to Table 26-2) in the user row. Once BOOTPROT is defined and after the next reboot, the content of the section becomes write-protected from the debugger or the processor write accesses.