26.5.7 Cache

The NVM Controller cache reduces the device power consumption and improves system performance when wait states are required. The NVM main array and the Data Flash address spaces are cached. It is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing a '0' to the Cache Disable bit in the Control B register (CTRLB.CACHEDIS).

The cache can be configured to three different modes using the Read Mode bit group in the Control B register (CTRLB.READMODE).

The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines (CTRLA.CMD = INVALL). Commands affecting NVM content automatically invalidate cache lines.