21.11.1 TC2 Control Register A
| Name: | TCCR2A |
| Offset: | 0xB0 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COM2A[1:0] | COM2B[1:0] | WGM2[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 7:6 – COM2A[1:0] Compare Output Mode for Channel A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A[1:0] bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the WGM2[2:0] bit setting. The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to a normal or CTC mode (non-PWM).
| COM2A[1] | COM2A[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC2A disconnected. |
| 0 | 1 | Toggle OC2A on compare match. |
| 1 | 0 | Clear OC2A on compare match. |
| 1 | 1 | Set OC2A on compare match . |
The table below shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWM mode.
| COM2A[1] | COM2A[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC2A disconnected. |
| 0 | 1 |
WGM2[2:0]: Normal port operation, OC2A disconnected WGM2[2:1]: Toggle OC2A on compare match |
| 1 | 0 | Clear OC2A on compare match, set OC2A at BOTTOM (non-inverting mode) |
| 1 | 1 | Set OC2A on compare match, clear OC2A at BOTTOM (inverting mode) |
- A special case occurs when OCR2A equals TOP and COM2A[1] is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to phase correct PWM mode.
| COM2A[1] | COM2A[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC2A disconnected. |
| 0 | 1 |
WGM2[2 :0]: Normal port operation, OC2A disconnected. WGM2[2:1]: Toggle OC2A on compare match. |
| 1 | 0 | Clear OC2A on compare match when up-counting. Set OC2A on compare match when down-counting. |
| 1 | 1 | Set OC2A on compare match when up-counting. Clear OC2A on compare match when down-counting. |
- A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Phase Correct PWM Mode for details.
Bits 5:4 – COM2B[1:0] Compare Output Mode for Channel B
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B[1:0] bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B[1:0] bits depends on the WGM2[2:0] bit setting. The table shows the COM2B[1:0] bit functionality when the WGM2[2:0] bits are set to a normal or CTC mode (non- PWM).
| COM2B[1] | COM2B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC2B disconnected. |
| 0 | 1 | Toggle OC2B on compare match. |
| 1 | 0 | Clear OC2B on compare match. |
| 1 | 1 | Set OC2B on compare match. |
The table below shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode.
| COM2B[1] | COM2B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0B disconnected. |
| 0 | 1 | Reserved |
| 1 | 0 | Clear OC0B on compare match, set OC0B at BOTTOM, (non-inverting mode) |
| 1 | 1 | Set OC0B on compare match, clear OC0B at BOTTOM, (inverting mode) |
- A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details.
The table below shows the COM2B[1:0] bit functionality when the WGM2[2:0] bits are set to phase correct PWM mode.
| COM2B[1] | COM2B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC2B disconnected. |
| 0 | 1 | Reserved |
| 1 | 0 | Clear OC2B on compare match when up-counting. Set OC2B on compare match when down-counting. |
| 1 | 1 | Set OC2B on compare match when up-counting. Clear OC2B on compare match when down-counting. |
- A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Phase Correct PWM Mode for details.
Bits 1:0 – WGM2[1:0] Waveform Generation Mode
Combined with the WGM2[2] bit found in the TCCR2B register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see Modes of Operation).
| Mode | WGM2[2] | WGM2[1] | WGM2[0] | Timer/Counter Mode of Operation | TOP | Update of OCR0x at | TOV Flag Set on(1) |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Normal | 0xFF | Immediate | MAX |
| 1 | 0 | 0 | 1 | PWM, Phase Correct | 0xFF | TOP | BOTTOM |
| 2 | 0 | 1 | 0 | CTC | OCR2A | Immediate | MAX |
| 3 | 0 | 1 | 1 | Fast PWM | 0xFF | BOTTOM | MAX |
| 4 | 1 | 0 | 0 | Reserved | - | - | - |
| 5 | 1 | 0 | 1 | PWM, Phase Correct | OCR2A | TOP | BOTTOM |
| 6 | 1 | 1 | 0 | Reserved | - | - | - |
| 7 | 1 | 1 | 1 | Fast PWM | OCR2A | BOTTOM | TOP |
- MAX = 0xFF
- BOTTOM = 0x00