13.12.1 Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.

The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: SMCR
Offset: 0x53
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x33

Bit 76543210 
     SM[2:0]SE 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 3:1 – SM[2:0] Sleep Mode Select

The SM[2:0] bits select between the five available sleep modes.

Table 13-2. Sleep Mode Select
SM[2:0]Sleep Mode
000Idle
001ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby(1)
111Extended Standby(1)
Note:
  1. Standby mode is only recommended for use with external crystals or resonators.

Bit 0 – SE Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.