13.12.3 Power Reduction Register 0


Bit	7	6	5	4	3	2	1	0
	PRTWI0	PRTIM2	PRTIM0	PRUSART1	PRTIM1	PRSPI0	PRUSART0	PRADC
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – PRTWI0 Power Reduction TWI0

Writing a logic one to this bit shuts down the TWI 0 by stopping the clock to the module. When waking up the TWI again, the TWI should be reinitialized to ensure proper operation.

Bit 6 – PRTIM2 Power Reduction Timer/Counter2

Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the Timer/Counter2 is enabled, the operation will continue like before the shutdown.

Bit 5 – PRTIM0 Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, the operation will continue like before the shutdown.

Bit 4 – PRUSART1 Power Reduction USART1

Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be reinitialized to ensure proper operation.

Bit 3 – PRTIM1 Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, the operation will continue like before the shutdown.

Bit 2 – PRSPI0 Power Reduction Serial Peripheral Interface 0

If using debugWIRE on-chip debug system, this bit should not be written to one. Writing a logic one to this bit shuts down the Serial Peripheral Interface (SPI) by stopping the clock to the module. When waking up the SPI again, the SPI should be reinitialized to ensure proper operation.

Bit 1 – PRUSART0 Power Reduction USART0