5.3 Configuring MIPI DSI

Module selection: Add the MIPI DSI driver to the project graph and link it to the SAMA7D65 DSI controller.

Parameters:

Lane count: Use two data lanes for High-Speed (HS) mode to maximize bandwidth
Transmission type: Non-burst with sync pulses
Clock configuration: Set the DSI PLL to generate 1 GHz (lane bit rate)

Lane bit rate calculation:

Calculate the actual lane bit rate and the total DSI bandwidth required for the display using:

Step 1: Calculate the total data rate

The total pixel rate is:

T o t a l P i x e l R a t e = 83.33 M H z = 83.33 \times 10^{6} p i x e l s / s e c

Since each pixel is 24 bits (3 bytes) for RGB, the required raw data rate is:

T o t a l D a t a R a t e = 83.33 \times 10^{6} \times 24

= 1.9999 G b p s \approx 2.0 G b p s (a p p r o x)

Step 2: Calculate per lane bit rate

Since the display operates with 2 lanes, the total data rate is split evenly:

L a n e B i t R a t e = \frac{T o t a l D a t a R a t e}{N u m b e r o f L a n e s}

= \frac{2.0 G b p s}{2}

= 1.0 G b p s (o r 1000 M b p s p e r l a n e)

This value is configured in the DSI driver module present in the project graph in MPLAB Harmony.