When the Timer1 value reaches the OCR1C value (0xFF), the Timer Overflow interrupt
service routine (ISR) is executed. This happens at a constant interval, since OCR1C
is constant. This interval is the base frequency of the fast PWM output signal.
The sine table generated as explained in Sine Wave Generation is stored in the Flash memory as a Look-Up Table.
When the ISR is executed, the value from sine table is loaded to OCR1A register. On
each look-up the index to the look-up table is incremented so that consecutive
values can be loaded. In this way the pulse width is modulated to the sine wave.
Note: The OCR1A register is
buffered and that the latching of the buffer into the actual OCR1A register
takes place on the timer overflow.
The interrupt routine in assembly language takes 13 clock cycles to
execute. The call to and return from the interrupt comes in addition – in total 21
system clock cycles. Since Timer1 is an 8-bit timer with top value as 255, the
interrupt occurs every TimerTop / (TimerFreq / CPUFreq) > 256 / 2 = 128
cycles.
If the Timer1 clock is configured to 64MHz and CPU is operated at 8MHz,
timer overflow interrupt occurs every 32 cycles of system clock (which is within the
limits of the application). Though it is possible to clock the Timer1 with the
maximum frequency of 64MHz, the PLL output is prescaled by 4 to 16MHz, to illustrate
the use of the prescaler.Figure 3-3. Flowchart of OC1A_isr() -
Timer1 ISR to Load Sine Table in OCR1A
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