17.7.3 External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk_T0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. See also the block diagram of the T0 synchronization and edge detector logic below. The registers are clocked at the positive edge of the internal system clock (clk_I/O). The latch is transparent in the high period of the internal system clock.

The edge detector generates one clk_T0 pulse for each positive (CS0[2:0]=0x7) or negative (CS0[2:0]=0x6) edge it detects.

Note: The “n” indicates the device number (n = 0 for Timer/Counter 0)

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f_ExtClk < f_{clk_I/O}/2) given a 50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by the tolerances of the oscillator source (crystal, resonator, and capacitors), it is recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.