48.6.14 MCAN Protocol Status Register
| Name: | MCAN_PSR |
| Offset: | 0x44 |
| Reset: | 0x00000707 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TDCV[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PXE | RFDF | RBRS | RESI | DLEC[2:0] | |||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 1 | 1 | 1 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BO | EW | EP | ACT[1:0] | LEC[2:0] | |||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
Bits 22:16 – TDCV[6:0] Transmitter Delay Compensation Value
0 to 127: Position of the secondary sample point, in CAN core clock periods, defined by the sum of the measured delay from CANTX to CANRX and MCAN_TDCR.TDCO.
Bit 14 – PXE Protocol Exception Event (cleared on read)
| Value | Description |
|---|---|
| 0 | No protocol exception event occurred since last read access |
| 1 | Protocol exception event occurred |
Bit 13 – RFDF Received a CAN FD Message (cleared on read)
This bit is set independently from acceptance filtering.
| Value | Description |
|---|---|
| 0 | Since this bit was reset by the CPU, no CAN FD message has been received |
| 1 | Message in CAN FD format with FDF flag set has been received |
Bit 12 – RBRS BRS Flag of Last Received CAN FD Message (cleared on read)
This bit is set together with RFDF, independently from acceptance filtering.
| Value | Description |
|---|---|
| 0 | Last received CAN FD message did not have its BRS flag set. |
| 1 | Last received CAN FD message had its BRS flag set. |
Bit 11 – RESI ESI Flag of Last Received CAN FD Message (cleared on read)
This bit is set together with RFDF, independently from acceptance filtering.
| Value | Description |
|---|---|
| 0 | Last received CAN FD message did not have its ESI flag set. |
| 1 | Last received CAN FD message had its ESI flag set. |
Bits 10:8 – DLEC[2:0] Data Phase Last Error Code (set to 111 on read)
Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
Bit 7 – BO Bus_Off Status
| Value | Description |
|---|---|
| 0 | The MCAN is not Bus_Off. |
| 1 | The MCAN is in Bus_Off state. |
Bit 6 – EW Warning Status
| Value | Description |
|---|---|
| 0 | Both error counters are below the Error_Warning limit of 96. |
| 1 | At least one of error counter has reached the Error_Warning limit of 96. |
Bit 5 – EP Error Passive
| Value | Description |
|---|---|
| 0 | The MCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected. |
| 1 | The MCAN is in the Error_Passive state. |
Bits 4:3 – ACT[1:0] Activity
Monitors the CAN communication state of the CAN module.
| Value | Name | Description |
|---|---|---|
| 0 | SYNCHRONIZING | Node is synchronizing on CAN communication |
| 1 | IDLE | Node is neither receiver nor transmitter |
| 2 | RECEIVER | Node is operating as receiver |
| 3 | TRANSMITTER | Node is operating as transmitter |
Bits 2:0 – LEC[2:0] Last Error Code (set to 111 on read)
The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared when a message has been transferred (reception or transmission) without error.
| Value | Name | Description |
|---|---|---|
| 0 | NO_ERROR | No error occurred since LEC has been reset by successful reception or transmission. |
| 1 | STUFF_ERROR | More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. |
| 2 | FORM_ERROR | A fixed format part of a received frame has the wrong format. |
| 3 | ACK_ERROR | The message transmitted by the MCAN was not acknowledged by another node. |
| 4 | BIT1_ERROR | During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant. |
| 5 | BIT0_ERROR | During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). |
| 6 | CRC_ERROR | The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. |
| 7 | NO_CHANGE | Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows value ‘7’, no CAN bus event was detected since the last processor read access to the Protocol Status Register. |