48.6.1 MCAN Core Release Register
Note: For revision A silicon the reset value
is 0x30130506.
| Name: | MCAN_CREL |
| Offset: | 0x00 |
| Reset: | 0x32150320 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| REL[3:0] | STEP[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SUBSTEP[3:0] | YEAR[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MON[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DAY[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
Bits 31:28 – REL[3:0] Core Release
One digit, BCD-coded.
Bits 27:24 – STEP[3:0] Step of Core Release
One digit, BCD-coded.
Bits 23:20 – SUBSTEP[3:0] Sub-step of Core Release
One digit, BCD-coded.
Bits 19:16 – YEAR[3:0] Timestamp Year
One digit, BCD-coded. This field is set by generic parameter on MCAN synthesis.
Bits 15:8 – MON[7:0] Timestamp Month
Two digits, BCD-coded. This field is set by generic parameter on MCAN synthesis.
Bits 7:0 – DAY[7:0] Timestamp Day
Two digits, BCD-coded. This field is set by generic parameter on MCAN synthesis.