48.6.5 MCAN Test Register
Write access to the Test Register has to be enabled by setting bit MCAN_CCCR.TEST to ‘1’.
All MCAN Test Register functions are set to their reset values when bit MCAN_CCCR.TEST is cleared.
Loop Back mode and software control of pin CANTX are hardware test modes. Programming of TX ≠ 0 disturbs the message transfer on the CAN bus.
The reset value for MCAN_TEST.RX is undefined.
| Name: | MCAN_TEST |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RX | TX[1:0] | LBCK | |||||||
| Access | R | R/W | R/W | R/W | |||||
| Reset | x | 0 | 0 | 0 | |||||
Bit 7 – RX Receive Pin (read-only)
Monitors the actual value of pin CANRX.
The reset value for this bit is undefined.
| Value | Description |
|---|---|
| 0 | The CAN bus is dominant (CANRX = ‘0’). |
| 1 | The CAN bus is recessive (CANRX = ‘1’). |
Bits 6:5 – TX[1:0] Control of Transmit Pin (read/write)
| Value | Name | Description |
|---|---|---|
| 0 | RESET | Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. |
| 1 | SAMPLE_POINT_MONITORING | Sample Point can be monitored at pin CANTX. |
| 2 | DOMINANT | Dominant (‘0’) level at pin CANTX. |
| 3 | RECESSIVE | Recessive (‘1’) at pin CANTX. |
Bit 4 – LBCK Loop Back Mode (read/write)
0 (DISABLED): Reset value. Loop Back mode is disabled.
1 (ENABLED): Loop Back mode is enabled (see Test Modes).