48.6.11 MCAN Timeout Counter Configuration Register
This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
For a description of the Timeout Counter, see Timeout Counter.
| Name: | MCAN_TOCC |
| Offset: | 0x28 |
| Reset: | 0xFFFF0000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TOP[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TOP[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TOS[1:0] | ETOC | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 31:16 – TOP[15:0] Timeout Period
Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
Bits 2:1 – TOS[1:0] Timeout Select
When operating in Continuous mode, a write to MCAN_TOCV presets the counter to the value configured by MCAN_TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by MCAN_TOCC.TOP. Down-counting is started when the first FIFO element is stored.
| Value | Name | Description |
|---|---|---|
| 0 | CONTINUOUS | Continuous operation. |
| 1 | TX_EV_TIMEOUT | Timeout controlled by Tx Event FIFO. |
| 2 | RX0_EV_TIMEOUT | Timeout controlled by Receive FIFO 0. |
| 3 | RX1_EV_TIMEOUT | Timeout controlled by Receive FIFO 1. |
Bit 0 – ETOC Enable Timeout Counter
0 (NO_TIMEOUT): Timeout Counter disabled.
1 (TOS_CONTROLLED): Timeout Counter enabled.
For use of timeout function with CAN FD, see Timeout Counter.