47.7.7 MediaLB Control 1 Register
| Name: | MLB_MLBC1 |
| Offset: | 0x03C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NDA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKM | LOCK | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bits 15:8 – NDA[7:0] Node Device Address
Used for system commands directed to individual MediaLB nodes.
Bit 7 – CLKM MediaLB Clock Missing Status (cleared by writing a 0)
Set when MLBCLK (MediaLB clock) is not toggling at the pin; cleared by software.
Bit 6 – LOCK MediaLB Lock Error Status (cleared by writing a 0)
Set when MediaLB is unlocked; cleared by software.