47.7.9 HBI Channel Mask 0 Register

The HC can control which channel(s) are able to generate an HBI interrupt by writing the HBI Channel Mask Registers (HCMRn). Each bit of HCMRn is read/write.

Name:	MLB_HCMR0
Offset:	0x088
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	CHM: Bitwise Channel Mask Bit [31[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CHM: Bitwise Channel Mask Bit [31[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CHM: Bitwise Channel Mask Bit [31[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CHM: Bitwise Channel Mask Bit [31[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – CHM: Bitwise Channel Mask Bit [31[31:0] 0]

CHM[n] = 1 indicates that channel n can generate an interrupt.