47.7.6 MediaLB Interrupt Enable Register

Name:	MLB_MIEN
Offset:	0x02C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
			CTX_BREAK	CTX_PE	CTX_DONE	CRX_BREAK	CRX_PE	CRX_DONE
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
		ATX_BREAK	ATX_PE	ATX_DONE	ARX_BREAK	ARX_PE	ARX_DONE	SYNC_PE
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
							ISOC_BUFO	ISOC_PE
Access							R/W	R/W
Reset							0	0

Bit 29 – CTX_BREAK Control Tx Break Enable

Value	Description
1	A ReceiverBreak response received from the receiver on a control Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 28 – CTX_PE Control Tx Protocol Error Enable

Value	Description
1	A ProtocolError generated by the receiver on a control Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 27 – CTX_DONE Control Tx Packet Done Enable

Value	Description
1	A packet transmitted with no errors on a control Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 26 – CRX_BREAK Control Rx Break Enable

Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Value	Description
1	A ControlBreak command received from the transmitter on a control.

Bit 25 – CRX_PE Control Rx Protocol Error Enable

Value	Description
1	A ProtocolError detected on a control Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 24 – CRX_DONE Control Rx Packet Done Enable

Value	Description
1	A packet received with no errors on a control Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 22 – ATX_BREAK Asynchronous Tx Break Enable

Value	Description
1	A ReceiverBreak response received from the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 21 – ATX_PE Asynchronous Tx Protocol Error Enable

Value	Description
1	A ProtocolError generated by the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 20 – ATX_DONE Asynchronous Tx Packet Done Enable

Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Value	Description
1	A packet transmitted with no errors on an asynchronous

Bit 19 – ARX_BREAK Asynchronous Rx Break Enable

Value	Description
1	A AsyncBreak command received from the transmitter on an asynchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 18 – ARX_PE Asynchronous Rx Protocol Error Enable

Value	Description
1	A ProtocolError detected on an asynchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 17 – ARX_DONE Asynchronous Rx Done Enable

Value	Description
1	A packet received with no errors on an asynchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 16 – SYNC_PE Synchronous Protocol Error Enable

Value	Description
1	A ProtocolError detected on a synchronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

Bit 1 – ISOC_BUFO Isochronous Rx Buffer Overflow Enable

Value	Description
1	A buffer overflow on an isochronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set. This occurs only when isochronous flow control is disabled.

Bit 0 – ISOC_PE Isochronous Rx Protocol Error Enable

Value	Description
1	A ProtocolError detected on an isochronous Rx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.

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