51.6.3 Conversion Resolution

The AFEC supports 12-bit native resolutions. Writing ‘2’ or greater to the RES field in the Extended Mode register (AFEC_EMR) automatically enables the Enhanced Resolution mode. For details on this mode, see 51.6.14 Enhanced Resolution Mode and Digital Averaging Function.

Moreover, when a DMA channel is connected to the AFEC, a resolution lower than 16 bits sets the transfer request size to 16 bits.

Note: If ADTRG is asynchronous to the AFEC peripheral clock, the internal resynchronization introduces a jitter of 1 peripheral clock. This jitter may reduce the resolution of the converted signal. Refer to the formula below, where f_IN is the frequency of the analog signal to convert and t_J is the half-period of 1 peripheral clock.

SNR = 20 \times \log 10 (\frac{1}{2 π f_{IN} t_{J}})