51.6.18 Register Write Protection
To prevent any single software error from corrupting AFEC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the AFEC Write Protection Mode Register (AFEC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the AFEC Write Protection Status Register (AFEC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS flag is automatically cleared by reading the AFEC_WPSR.
The protected registers are:
- AFEC Mode Register
- AFEC Extended Mode Register
- AFEC Channel Sequence 1 Register
- AFEC Channel Sequence 2 Register
- AFEC Channel Enable Register
- AFEC Channel Disable Register
- AFEC Compare Window Register
- AFEC Channel Gain 1 Register
- AFEC Channel Differential Register
- AFEC Channel Selection Register
- AFEC Channel Offset Compensation Register
- AFEC Temperature Sensor Mode Register
- AFEC Temperature Compare Window Register
- AFEC Analog Control Register
- AFEC Sample & Hold Mode Register
- AFEC Correction Select Register
- AFEC Correction Values Register
- AFEC Channel Error Correction Register