45.6.8 SPI Mode

The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with external devices in Host or Client mode. It also enables communication between processors if an external processor is connected to the system.

The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “Host” which controls the data flow, while the other devices act as “Clients'' which have data shifted into and out by the Host. Different CPUs can take turns being Hosts and one Host may simultaneously shift data into multiple Clients. (Multiple Host protocol is the opposite of single Host protocol, where one CPU is always the Host while all of the others are always Clients.) However, only one Client may drive its output to write data back to the Host at any given time.

A Client device is selected when its NSS signal is asserted by the Host. The USART in SPI Host mode can address only one SPI Client because it can generate only one NSS signal.

The SPI system consists of two data lines and two control lines:

• Host Out Client In (MOSI): This data line supplies the output data from the Host shifted into the input of the Client.
• Host In Client Out (MISO): This data line supplies the output data from a Client to the input of the Host.
• Serial Clock (SCK): This control line is driven by the Host and regulates the flow of the data bits. The Host may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
• Client Select (NSS): This control line allows the Host to select or deselect the Client.