58.2 DC Characteristics

The following characteristics are applicable to the operating temperature range: T_A [-40°C : +105°C], unless otherwise specified.

Table 58-3. DC Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
V_DDCORE	DC Supply Core	–	1.08	1.2	1.32	V
	Allowable Voltage Ripple	rms value 10 kHz to 20 MHz	–	–	20	mV
	Rising Slope ⁽²⁾	–	1.9	–	30	V/ms
V_DDIO	DC Supply I/Os, Backup	(See Note 1)	1.7	3.3	3.6	V
	Allowable Voltage Ripple	rms value 10 kHz to 10 MHz	–	–	30	mV
	Rising Slope	–	1.9	–	30	V/ms
V_DDIN	DC Supply Voltage Regulator	(See Note 1)	1.7	3.3	3.6	V
V_DDIN	Allowable Voltage Ripple	rms value 10 kHz to 20 MHz	–	–	20	mv
V_DDPLL	PLL A and Main Oscillator Supply	–	1.08	1.2	1.32	V
	Allowable Voltage Ripple	rms value 10 kHz to 10 MHz	–	–	20	mV
	Allowable Voltage Ripple	rms value > 10 MHz	–	–	10	mV
V_DDUTMIC	DC Supply UDPHS and UHPHS UTMI+ Core	–	1.08	1.2	1.32	V
V_DDUTMIC	Allowable Voltage Ripple	rms value 10 kHz to 10 MHz	–	–	10	mV
V_DDUTMII	DC Supply UDPHS and UHPHS UTMI+ Interface	–	3.0	3.3	3.6	V
V_DDUTMII	Allowable Voltage Ripple	rms value 10 kHz to 10 MHz	–	–	20	mV
V_DDPLLUSB	DC Supply UTMI PLL	–	3.0	3.3	3.6	V
V_DDPLLUSB	Allowable Voltage Ripple	rms value 10 kHz to 10 MHz	–	–	10	mV

Note:

V_DDIO voltage must be equal to V_DDIN voltage.
Refer to section 7.2.1 Powerup.

Table 58-4. DC Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
V_IL	Low-level Input Voltage	GPIO_MLB	-0.3	–	0.7	V
		GPIO_AD, GPIO_CLK	-0.3	–	V_DDIO x 0.3
		GPIO, CLOCK, RST, TEST	-0.3	–	V_DDIO x 0.3
V_IH	High-level Input Voltage	GPIO_MLB	1.80	–	V_DDIO + 0.3	V
		GPIO_AD, GPIO_CLK	V_DDIO x 0.7		V_DDIO + 0.3
		GPIO, CLOCK, RST, TEST	V_DDIO x 0.7	–	V_DDIO + 0.3
V_OH	High-level Output Voltage	GPIO_MLB , IOH = 6 mA	2	–	–	V
		GPIO_AD, GPIO, RST, TEST, CLOCK ,IOH = 4 mA, Low drive	V_DDIO - 0.4	–	–
		GPIO_AD, GPIO, RST, TEST, CLOCK ,IOH = 10 mA, High drive	V_DDIO - 0.4	–	–
		GPIO_CLK, IOH = 6 mA, Low drive	V_DDIO - 0.4
		GPIO_CLK, IOH = 12 mA, High drive	V_DDIO - 0.4	–	–
V_OL	Low-level Output Voltage	GPIO_MLB, IOL = -6 mA	–	–	0.4	V
		GPIO_AD, GPIO, RST, TEST, CLOCK, IOL = -4 mA, Low drive	–	–	0.4
		GPIO_AD, GPIO, RST, TEST, CLOCK, IOL = -10 mA,High drive	–	–	0.4
		GPIO_CLK, IOL = -6 mA, Low drive	–	–	0.4
		GPIO_CLK, IOL = -12 mA, High drive	–	–	0.4
V_hys	Hysteresis Voltage	GPIO with Hysteresis mode enabled	150	–	–	mV
I_IL	Low-level Input Current	Pullup OFF	-1	–	1	µA
I_IL	Low-level Input Current	Pullup ON	10	–	55	µA
I_IH	High-level Input Current	Pulldown OFF	-1	–	1	µA
I_IH	High-level Input Current	Pulldown ON	10	–	55	µA
R_SERIAL	Serial Resistor	GPIO_MLB	–	9	–	Ohm
		GPIO_AD, GPIO_CLK	–	14	–
		GPIO, CLOCK, RST, TEST	–	26	–

Table 58-5. Voltage Regulator Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
V_DDOUT	DC Output Voltage	Normal mode, I_LOAD = 100 mA	1.2	1.23	1.26	V
V_DDOUT	DC Output Voltage	Standby mode	–	0	–	V
I_LOAD	Maximum DC Output Current		–	–	150	mA
C_DIN	Input Decoupling Capacitor	(1)	–	4.7	–	µF
C_DOUT	Output Decoupling Capacitor	(2)	–	1	–	µF
C_DOUT	Output Decoupling Capacitor	ESR	–	–	2	Ohm
t_ON	Turn-on Time	C_DOUT = 1 µF, V_DDOUT reaches DC output voltage	–	1	2.5	ms

Note: 1. A 4.7 μF (±20%) or higher ceramic capacitor must be connected between V_DDIN and the closest GND pin of the device. This large decoupling capacitor is mandatory to reduce startup current, improving transient response and noise rejection.

Note: 2. To ensure stability, an external 1 μF (±20%) output capacitor, C_DOUT, must be connected between V_DDOUT and the closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitors. A 100 nF bypass capacitor between V_DDOUT and the closest GND pin of the device helps decrease output noise and improves the load transient response.

Table 58-6. Core Power Supply Brownout Detector Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
V_T-	Supply Falling Threshold (see Note 1)	–	0.97	1.0	1.04	V
V_hys	Hysteresis Voltage	–	–	25	50	mV
t_START	Startup Time	From disabled state to enabled state	–	–	400	µs

Note: 1. The Brown-out Detector (BOD) is configured using the BODDIS bit in the SUPC_MR register.

Figure 58-1. Core Brownout Output Waveform

Table 58-7. VDDCORE Power-on Reset (POR) Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
V_T+	Threshold Voltage Rising	–	0.79	0.95	1.07	V
V_T-	Threshold Voltage Falling	–	0.66	0.89	–	V
V_hys	Hysteresis Voltage	–	10	60	115	mV
t_RES	Reset Timeout Period	–	240	350	800	µs

Figure 58-2. VDDCORE Power-On Reset Characteristics

Table 58-8. VDDIO Supply Monitor
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
V_T	Supply Monitor Threshold	16 selectable steps (see the Threshold Selection table below)	–	–	–	V
T_ACC	Threshold Accuracy	–	-4	–	4	%
V_hys	Hysteresis Voltage	–	–	38	45	mV
t_START	Startup Time	From disabled state to enabled state	–	–	300	µs

Note:

There are several mechanisms to hold the device in RESET during a power down cycle to ensure correct operation. The first monitor that will get triggered will be the Supply Monitor which is triggered at the Supply Monitor Threshold. The Supply Monitor will hold the device in RESET until POR Monitor activates and holds the device in RESET until the power-down cycle is complete. Therefore, it is recommended to enable the Supply Monitor, see Table 59-9 Threshold Selection.
The Supply Monitor operates down to 1.7V.
Once the Supply Monitor threshold is reached, it takes <200 µs to generate the internal reset of the device. The internal reset will remain active all the way until the POR becomes active.
The 200 us reset time parameter is for design guidance only and is not tested in manufacturing.

Table 58-9. Threshold Selection
Symbol	Parameter	Digital Code	Min.	Typ.	Max.	Unit
V_T	Supply Monitor Threshold	0	–	1.6	–	V
		1	–	1.72	–
		10	–	1.84	–
		11	–	1.96	–
		100	–	2.08	–
		101	–	2.2	–
		110	–	2.32	–
		111	–	2.44	–
		1000	–	2.56	–
		1001	–	2.68	–
		1010	–	2.8	–
		1011	–	2.92	–
		1100	–	3.04	–
		1101	–	3.16	–
		1110	–	3.28	–
		1111	–	3.4	–

Table 58-10. VDDIO Power-On Reset DC Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
V_T+	Threshold Voltage Rising	–	1.45	1.53	1.61	V
V_T-	Threshold Voltage Falling	–	1.37	1.46	–	V
V_hys	Hysteresis	–	40	80	130	mV
t_RES	Reset Time-out Period	–	240	320	800	µs

Figure 58-4. VDDIO Power-On Reset Characteristics