58.11 12-bit DAC Characteristics

Table 58-42. Analog Power Supply Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
I_VDDIN	Current Consumption	Sleep mode (Clock OFF)	–	10	–	µA
		Normal mode with one output on, DACC_ACR.IBCTLCHx =3 (see Note 1) FS = 1 MSps, no R_LOAD, V_DDIN = 3.3V	–	200	800
		Normal mode with one output on, DACC_ACR.IBCTLCHx =1 (see Note 1) FS = 500 KSps, no R_LOAD, V_DDIN = 3.3V	–	100	400
		Bypass mode (output buffer off) with one output on, DACC_ACR.IBCTLCHx =0 (see Note 1) FS = 500 KSps, no R_LOAD, V_DDIN = 3.3V	–	10	30
PSRR	Power Supply RejectionRatio (V_DDIN)	V_DDIN ±10 mV Up to 10 kHz	–	70	–	dB

Note: 1. The maximum conversion rate versus the configuration of DACC_ACR.IBCTL is shown in the following table.

Table 58-43. Maximum Conversion Rate vs. Configuration of DACC_ACR.IBCTL
DACC_ACR.IBCTLCHx	Maximum Conversion Rate
0	Bypass
1	500 ks/s
2	N/A
3	1 Ms/s

Table 58-44. Voltage Reference
Symbol	Parameter	Conditions		Min.	Typ.	Max.	Unit
V_VREFP	Positive Voltage Reference	Externally decoupled 1 µF		1.7	–	V_DDIN	V
I_VREFP	DC Current on VREFP	–		–	2.5	–	µA

Note: V_REFP is the positive reference shared with AFE and may have a different value for AFE. Refer to the AFE electrical characteristics if AFE is used. The V_REFN pin must be connected to ground.

Table 58-45. DAC Clock
Symbol	Parameter	Conditions		Min.	Typ.	Max.	Unit
f_DAC	DAC Clock Frequency	–		–	–	12	MHz
f_S	Sampling Frequency	–		–	f_DAC/ 12	–	MHz

Table 58-46. Static Performance Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
INL	Integral Non-linearity (see Note 1)	No R_LOAD	-10	±2	10	LSB
		C_LOAD = 50 pF
		DACC_ACR.IBTLCHx = 3
DNL	Differential Non-linearity (see Note 1)	No R_LOAD	-4	±2	4	LSB
		C_LOAD = 50 pF
		DACC_ACR.IBTLCHx = 3
E_O	Offset Error (see Note 2)	–	-8	1	8	mV
E_G	Gain Error	No R_LOAD	-1	–	1	%.FSR
		C_LOAD = 50 pF
		DACC_ACR.IBTLCHx = 3

Note:

Best-fit Curve from 0x080 to 0xF7F.
Difference between DACx at 0x800 and V_VREFP/2.

Table 58-47. Dynamic Performance Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
t_START	Startup Time	From DAC on (CHER.CHx) to DAC ready to convert (CHSR.DACRDYx)	–	10	–	µs
t_S	Settling Time Code to Code; i.e., code(n-1) to code(n) ± 0.5 LSB	R_LOAD = 5 Kohm C_LOAD = 50 pF	–	0.5	–	µs
	Settling Time Full-scale; i.e., 0x000 to 0xFFF ±0.5 LSB	DACC_ACR.IBCTLCHx = 3	–	1	–	µs
	Settling Time Full-scale; i.e., 0x000 to 0xFFF ±0.5 LSB	FS = 1 MSps	–	1	–	µs
Slew Rate			–	3	–	V/µs

Table 58-48. Analog Outputs
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
R_LOAD	Output Resistor Load	Output load resistor	5	–	–	kOhm
C_LOAD	Output Capacitor Load	Output load capacitor	–	–	50	pF
V_{DACx_MIN}	Minimum Output Voltage on DACx	Code = 0x000 No R_LOAD, C_LOAD = 50 pF, DACC_ACR.IBCTLCHx =3	–	0.1	0.5	%. V_VREFP
V_{DACx_MAX}	Maximum Output Voltage on DACx	Code = 0xFFF No R_LOAD C_LOAD = 50 pF, DACC_ACR.IBCTLCHx =3	99.5	99.9	–	%. V_VREFP
FSR	Full Scale Range	Code = 0x000 to 0xFFF No R_LOAD C_LOAD= 50 pF, DACC_ACR.IBCTLCHx =3	99	99.8	–	%. V_VREFP
R_OUT	DAC Output Resistor	0.3 < V_DACx < V_DDIN -0.3V, DACC_ACR.IBCTLCHx =3, R_LOAD= 5 KOhm	–	15	–	Ohm
		V_DACx > V_DDIN -0.3V, DACC_ACR.IBCTLCHx =3, R_LOAD= 5 kOhm	–	550	–	Ohm
		V_DACx < 0.3V, DACC_ACR.IBCTLCHx = 3, _RLOAD= 5 kOhm	–	550	–	Ohm
		V_DACx = V_VREFP/2, DACC_ACR.IBCTLCHx = 0 (Bypass mode, buffer off), No R_LOAD	–	300	–	kOhm