57.3.4 Active Mode Power Consumption
The conditions for measurement are defined as follows:
- VDDIO = VDDIN = 3.3V
- VDDCORE is provided by the Internal Voltage Regulator
- TA = 25°C
- Application running from Flash memory with 128-bit access mode
- All peripheral clocks are deactivated.
- Host Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator.
- Current measurement on AMP1 (VDDCORE) and total current on AMP2
The following table gives current consumption in Active mode in typical conditions.
| Core Clock/MCK (MHz) | Cortex-M7 Running CoreMark | Unit | ||
|---|---|---|---|---|
| Flash | TCM | |||
| Cache Enable (CE) CoreMark = 4.9/MHz | Cache Disable (CD) CoreMark = 1.0/MHz | CoreMark = 5.0/MHz | ||
| 300/150 | 90 | 57 | 83 | mA |
| 250/125 | 77 | 48 | 70 | |
| 150/150 | 52 | 40 | 48 | |
| 96/96 | 35 | 27 | 33 | |
| 96/48 | 31 | 20 | 28 | |
| 48/48 | 18 | 15 | 17 | |
| 24/24 | 10 | 8 | 9 | |
| 24/12 | 9 | 6 | 8 | |
| 12/12 | 5 | 4 | 5 | |
| 8/8 | 4 | 3 | 4 | |
| 4/4 | 2 | 2 | 2.5 | |
| 4/2 | 2 | 1.5 | 2 | |
| 4/1 | 1.5 | 1.5 | 1.5 | |
| 2/2 | 1.5 | 1.5 | 1.5 | |
Note: Flash Wait State (FWS) in EEFC_FMR is adjusted depending on core frequency.