44.8.4 I2SC Status Clear Register

Name: I2SC_SCR
Offset: 0x0C
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   TXURCH[1:0]     
Access WW 
Reset –– 
Bit 15141312111098 
       RXORCH[1:0] 
Access WW 
Reset –– 
Bit 76543210 
  TXUR   RXOR   
Access WW 
Reset –– 

Bits 21:20 – TXURCH[1:0] Transmit Underrun Per Channel Status Clear

Writing a ’0’ has no effect.

Writing a ’1’ to any bit in this field clears the corresponding bit in the I2SC_SR and the corresponding interrupt request.

Bits 9:8 – RXORCH[1:0] Receive Overrun Per Channel Status Clear

Writing a ’0’ has no effect.

Writing a ’1’ to any bit in this field clears the corresponding bit in the I2SC_SR and the corresponding interrupt request.

Bit 6 – TXUR Transmit Underrun Status Clear

Writing a ’0’ to this bit has no effect.

Writing a ’1’ to this bit clears the status bit.

Bit 2 – RXOR Receive Overrun Status Clear

Writing a ’0’ to this bit has no effect.

Writing a ’1’ to this bit clears the status bit.