44.8.1 I2SC Control Register
| Name: | I2SC_CR |
| Offset: | 0x00 |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | TXDIS | TXEN | CKDIS | CKEN | RXDIS | RXEN | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
Bit 7 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | Writing a ’0’ to this bit has no effect. |
| 1 | Writing a ’1’ to this bit resets all the registers in the I2SC. The I2SC is disabled after the reset. |
Bit 5 – TXDIS Transmitter Disable
| Value | Description |
|---|---|
| 0 | Writing a ’0’ to this bit has no effect. |
| 1 | Writing a ’1’ to this bit disables the I2SC transmitter. Bit I2SC_SR.TXEN is cleared when the Transmitter is stopped. |
Bit 4 – TXEN Transmitter Enable
| Value | Description |
|---|---|
| 0 | Writing a ’0’ to this bit has no effect. |
| 1 | Writing a ’1’ to this bit enables the I2SC transmitter, if TXDIS is not one. Bit I2SC_SR.TXEN is set when the Transmitter is started. |
Bit 3 – CKDIS Clocks Disable
| Value | Description |
|---|---|
| 0 | Writing a ’0’ to this bit has no effect. |
| 1 | Writing a zone to this bit disables the I2SC clock generation. |
Bit 2 – CKEN Clocks Enable
| Value | Description |
|---|---|
| 0 | Writing a ’0’ to this bit has no effect. |
| 1 | Writing a ’1’ to this bit enables the I2SC clocks generation, if CKDIS is not one. |
Bit 1 – RXDIS Receiver Disable
| Value | Description |
|---|---|
| 0 | Writing a ’0’ to this bit has no effect. |
| 1 | Writing a ’1’ to this bit disables the I2SC receiver. Bit I2SC_SR.RXEN is cleared when the receiver is stopped. |
Bit 0 – RXEN Receiver Enable
| Value | Description |
|---|---|
| 0 | Writing a ’0’ to this bit has no effect. |
| 1 | Writing a ’1’ to this bit enables the I2SC receiver, if RXDIS is not one. Bit I2SC_SR.RXEN is set when the receiver is activated. |