19.4.3 Bus Matrix Priority Registers A For Clients

This register can only be written if the WPE bit is cleared in the Write Protection Mode Register.

Name: MATRIX_PRASx
Offset: 0x80 + x*0x08 [x=0..8]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
   M7PR[1:0]  M6PR[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
   M5PR[1:0]  M4PR[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
   M3PR[1:0]  M2PR[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
   M1PR[1:0]  M0PR[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 0:1, 4:5, 8:9, 12:13, 16:17, 20:21, 24:25, 28:29 – MxPR Host x Priority

Fixed priority of Host x for accessing the selected Client. The higher the number, the higher the priority.

All the Hosts programmed with the same MxPR value for the Client make up a priority pool.

Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.

Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).

See “Arbitration Priority Scheme” for details.