52.7.10 DACC Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

Name: DACC_IMR
Offset: 0x2C
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   EOC1EOC0  TXRDY1TXRDY0 
Access RRRR 
Reset 0000 

Bits 4, 5 – EOCx End of Conversion Interrupt Mask of channel x

Bits 0, 1 – TXRDYx Transmit Ready Interrupt Mask of channel x