52.7.10 DACC Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Name: | DACC_IMR |
Offset: | 0x2C |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | EOC1 | EOC0 | | | TXRDY1 | TXRDY0 | |
Access | | | R | R | | | R | R | |
Reset | | | 0 | 0 | | | 0 | 0 | |
Bits 4, 5 – EOCx End of Conversion Interrupt Mask of channel x
Bits 0, 1 – TXRDYx Transmit Ready Interrupt Mask of channel x