52.7.3 DACC Trigger Register
This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
| Name: | DACC_TRIGR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OSR1[2:0] | OSR0[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRGSEL1[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRGSEL0[2:0] | TRGEN1 | TRGEN0 | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 16:18, 20:22 – OSRx Oversampling Ratio of Channel x
| Value | Name | Description |
|---|---|---|
| 0 | OSR_1 | OSR = 1 |
| 1 | OSR_2 | OSR = 2 |
| 2 | OSR_4 | OSR = 4 |
| 3 | OSR_8 | OSR = 8 |
| 4 | OSR_16 | OSR = 16 |
| 5 | OSR_32 | OSR = 32 |
Bits 4:6, 8:10 – TRGSELx Trigger Selection of Channel x
| Value | Name | Description |
|---|---|---|
| 0 | TRGSEL0 | DATRG |
| 1 | TRGSEL1 | TC0.Ch0 output |
| 2 | TRGSEL2 | TC0.Ch1 output |
| 3 | TRGSEL3 | TC0.Ch2 output |
| 4 | TRGSEL4 | PWM0 Event 0 |
| 5 | TRGSEL5 | PWM0 Event 1 |
| 6 | TRGSEL6 | PWM1 Event 0 |
| 7 | TRGSEL7 | PWM1 Event 1 |
Bits 0, 1 – TRGENx Trigger Enable of Channel x
| Value | Name | Description |
|---|---|---|
| 0 | DIS | Trigger mode disabled. DACC is in Free-running mode or Max speed mode. |
| 1 | EN | Trigger mode enabled. |