52.7.2 DACC Mode Register
This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
| Name: | DACC_MR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PRESCALER[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DIFF | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZERO | WORD | MAXS1 | MAXS0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 27:24 – PRESCALER[3:0] Peripheral Clock to DAC Clock Ratio
This field defines the division ratio between the peripheral clock and the DAC clock as per the following formula:
Bit 23 – DIFF Differential Mode
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | DAC0 and DAC1 are single-ended outputs. |
| 1 | ENABLED | DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. |
Bit 5 – ZERO Must always be written to 0.
Bit 4 – WORD Word Transfer Mode
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | One data to convert is written to the FIFO per access to DACC. |
| 1 | ENABLED | Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). |
Bits 0, 1 – MAXSx Max Speed Mode for Channel x
| Value | Name | Description |
|---|---|---|
| 0 | TRIG_EVENT | Trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) |
| 1 | MAXIMUM | Max speed mode enabled. |