32.6.53 PIO Parallel Capture Interrupt Mask RegisterThe following configuration values are valid for all listed bit names of this register:0: Corresponding interrupt is not enabled.1: Corresponding interrupt is enabled.Name: PIO_PCIMROffset: 0x015CReset: 0x00000000Property: Read-onlyBit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 Access Reset Bit 76543210 RXBUFFENDRXOVREDRDY Access RRRR Reset 0000 Bit 3 – RXBUFF Reception Buffer Full Interrupt Mask Bit 2 – ENDRX End of Reception Transfer Interrupt Mask Bit 1 – OVRE Parallel Capture Mode Overrun Error Interrupt Mask Bit 0 – DRDY Parallel Capture Mode Data Ready Interrupt Mask
Bit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 Access Reset Bit 76543210 RXBUFFENDRXOVREDRDY Access RRRR Reset 0000
