32.6.50 PIO Parallel Capture Mode Register

This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

Name: PIO_PCMR
Offset: 0x0150
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     FRSTSHALFSALWYS  
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
   DSIZE[1:0]   PCEN 
Access R/WR/WR/W 
Reset 000 

Bit 11 – FRSTS Parallel Capture Mode First Sample

This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an index from 0 to n:

ValueDescription
0 Only data with an even index are sampled.
1 Only data with an odd index are sampled.

Bit 10 – HALFS Parallel Capture Mode Half Sampling

Independently from the ALWYS bit:

ValueDescription
0 The Parallel Capture mode samples all the data.
1 The Parallel Capture mode samples the data only every other time.

Bit 9 – ALWYS Parallel Capture Mode Always Sampling

ValueDescription
0 The Parallel Capture mode samples the data when both data enables are active.
1 The Parallel Capture mode samples the data whatever the data enables are.

Bits 5:4 – DSIZE[1:0] Parallel Capture Mode Data Size

ValueNameDescription
0 BYTE The reception data in the PIO_PCRHR is a byte (8-bit)
1 HALF-WORD The reception data in the PIO_PCRHR is a half-word (16-bit)
2 WORD The reception data in the PIO_PCRHR is a word (32-bit)
3 Reserved Reserved

Bit 0 – PCEN Parallel Capture Mode Enable

ValueDescription
0 The Parallel Capture mode is disabled.
1 The Parallel Capture mode is enabled.