32.6.51 PIO Parallel Capture Interrupt Enable RegisterThe following configuration values are valid for all listed bit names of this register:0: No effect1: Enables the corresponding interruptName: PIO_PCIEROffset: 0x0154Property: Write-onlyBit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 Access Reset Bit 76543210 RXBUFFENDRXOVREDRDY Access WWWW Reset Bit 3 – RXBUFF Reception Buffer Full Interrupt Enable Bit 2 – ENDRX End of Reception Transfer Interrupt Enable Bit 1 – OVRE Parallel Capture Mode Overrun Error Interrupt Enable Bit 0 – DRDY Parallel Capture Mode Data Ready Interrupt Enable
Bit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 Access Reset Bit 76543210 RXBUFFENDRXOVREDRDY Access WWWW Reset
