37.8.103 GMAC Receive Buffer Queue Base Address Register Priority Queue x

These registers hold the start address of the receive buffer queues (receive buffers descriptor lists) for the additional queues used when priority queues are employed.

Name:	GMAC_RBQBAPQx
Offset:	0x0480 + (x-1)*0x04 [x=1..2]
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	RXBQBA[29:22]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RXBQBA[21:14]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RXBQBA[13:6]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RXBQBA[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0

Bits 31:2 – RXBQBA[29:0] Receive Buffer Queue Base Address

Holds the address of the start of the receive queue.