51.8.20 AFEC Channel Offset Compensation Register

This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.

Name:	AFEC_COCR
Offset:	0x6C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
							AOFF[9:8]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	AOFF[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 9:0 – AOFF[9:0] Analog Offset

Defines the analog offset to be used for channel CSEL (configured in the AFEC Channel Selection Register). This value is used as an input value for the DAC included in the AFE.

Note: The AOFF field must be configured to 512 (mid scale of the DAC) when there is no offset error to compensate. To compensate for an offset error of n LSB (positive or negative), the AOFF field must be configured to 512 + n.

The value of the AOFF bit can be updated only if the AFEC module is restarted, or if two conversions are run; the second one will have the correct AOFF bit setting.