6.1 STATUS Register Bit Definition and Function
The AT25512 includes an 8‑bit STATUS register. The
STATUS register bits modulate various features of the device as shown in Table 6-2 and
Table 6-3.
These bits can be changed by specific instructions that are detailed in the following
sections.
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|
| WPEN | X | X | X | BP1 | BP0 | WEL | RDY/BSY |
| Bit | Name | Type | Description | ||
|---|---|---|---|---|---|
| 7 | WPEN | Write-Protect Enable | R/W | 0 | See Table 6-5 (Factory Default) |
1 | See Table 6-5 (Factory Default) | ||||
| 6:4 | RFU | Reserved for Future Use | R | 0 | Reads as zeros when the device is not in a write cycle |
1 | Reads as ones when the device is in a write cycle | ||||
| 3:2 | BP1 BP0 | Block Write Protection | R/W | 00 | No array write protection (Factory Default) |
01 | Quarter array write protection (see Table 6-4) | ||||
10 | Half array write protection (see Table 6-4) | ||||
11 | Entire array write protection (see Table 6-4) | ||||
| 1 | WEL | Write Enable Latch | R | 0 | Device is not write enabled (Power-up Default) |
1 | Device is write enabled | ||||
| 0 | RDY/BSY | Ready/Busy Status | R | 0 | Device is ready for a new sequence |
1 | Device is busy with an internal operation | ||||