The Write STATUS Register (WRSR) instruction enables the SPI Host to change
selected bits of the STATUS register. Before a WRSR instruction can be
initiated, a WREN instruction must be executed to set the WEL bit to
logic ‘1’. Upon completion of a WREN instruction,
a WRSR instruction can be executed.
Note: The WRSR
instruction has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS
register. Only bit 7, bit 3 and bit 2 can be changed via the WRSR
instruction. These modifiable bits are the Write-Protect Enable (WPEN) and Block
Protect (BP1, BP0) bits. These three bits are nonvolatile bits that have the same
properties and functions as regular EEPROM cells. Their values are retained while
power is removed from the device.
The AT25512 will not respond to commands
other than a RDSR after a WRSR instruction until
the self‑timed internal write cycle has completed. When the write cycle is completed,
the WEL bit in the STATUS register is reset to logic ‘0’.Figure 6-4. WRSR Waveform
Note:
This instruction initiates a
self-timed internal write cycle (tWC) on the rising edge of
CS after a valid sequence.
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