Core Features

  • C Compiler Optimized RISC Architecture
  • Operating Speed:
    • DC – 32 MHz clock input
    • 125 ns minimum instruction cycle
  • Interrupt Capability
  • 16-Level Deep Hardware Stack
  • Up to Four 8-Bit Timers
  • Up to Four 16-Bit Timers
  • Low-Current Power-on Reset (POR)
  • Configurable Power-up Timer (PWRT)
  • Brown-out Reset (BOR)
  • Low-Power BOR (LPBOR) Option
  • Windowed Watchdog Timer (WWDT):
    • Variable prescaler selection
    • Variable window size selection
    • All sources configurable in hardware or software
  • Programmable Code Protection