36.11.6 Host Endpoint 1-7 Polling Interval Register

Table 36-83. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Name: TXINTERVAL
Offset: 0x101B
Reset: 0x0000
Property: PAC Write-Protection

Bit 76543210 
 TXPOLLINGINTERVAL[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – TXPOLLINGINTERVAL[7:0] Endpoint TX Polling Interval/NAK Limit bits (Host mode)

For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk end- points,this field sets the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses.

The following table describes the valid values and interpretation for these bits:

Transfer Type Speed Valid Values (m) Interpretation
Interrupt Low/Full 0x01 to 0xFF Polling interval is 'm' frames.
High 0x01 to 0x10 Polling interval is 2(m-1) frames.
Isochronous Full or High 0x01 to 0x10 Polling interval is 2(m-1) frames/microframes.
Bulk Full or High 0x02 to 0x10 NAK limit is 2(m-1) frames/microframes. A value of '0' or '1' disables the NAK time-out function.