36.11.1 TX Control Status Register Low for Endpoint 1-7
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TXCSRL |
| Offset: | 0x1012 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NAKTMOUT | CLRDATATOG | RXSTALL | SETUPPKT | FLUSHFIFO | ERROR | FIFONOTEMPTY | TXPKTRDY | ||
| Access | R/W/HS | R/W/HC | R/W | R/W | R/W | R/W/HC | R/W | R/W/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – NAKTMOUT NAK Time-out Status bit
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit |
| 1 | TX endpoint is halted following the receipt of NAK responses for longer than the NAKLIM setting |
Bit 6 – CLRDATATOG Clear Data Toggle Control Bit
| Value | Description |
|---|---|
| 0 | Do not clear the data toggle |
| 1 | Resets the endpoint data toggle to 0 |
Bit 5 – RXSTALL Stall Receipt Bit
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit |
| 1 | STALL handshake is received. Any DMA request in progress is stopped, the FIFO is completely flushed and the TXPKTRDY bit is cleared. |
Bit 4 – SETUPPKT Definition bit
| Value | Description |
|---|---|
| 0 | Normal OUT token for the transaction |
| 1 | When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token for the transaction. This also clears the Data Toggle. |
Bit 3 – FLUSHFIFO FIFO Flush Control bit
| Value | Description |
|---|---|
| 0 | Do not flush the FIFO |
| 1 | Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, the TXPKTRDY bit is cleared and an interrupt is generated. |
Bit 2 – ERROR Handshake Failure Status bit
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit. |
| 1 | Three attempts have been made to send a packet and no handshake packet has been received |
Bit 1 – FIFONOTEMPTY FIFO Not Empty Status bit
| Value | Description |
|---|---|
| 0 | TX FIFO is empty |
| 1 | There is at least 1 packet in the TX FIFO |
Bit 0 – TXPKTRDY TX Packet Ready Control bit
The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a double-buffered FIFO.