36.11.4 RX Control Status Register High for Endpoint 1-7
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RXCSRH |
| Offset: | 0x1017 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AUTOCLEAR | AUTOREQ | DMAREQENAB | PIDERROR | DMAREQMODE | DATATOGGLEWRENABLE | DATATOGGLE | INCOMPRX | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W/HC | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – AUTOCLEAR RXPKTRDY Automatic Clear Control bit
This bit should not be set for high-bandwidth Isochronous endpoints.
| Value | Description |
|---|---|
| 0 | No automatic clearing of RXPKTRDY |
| 1 | RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the RXFIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte chunks regardless of the RXMAXP. |
Bit 6 – AUTOREQ Automatic Packet Request Control bit
This bit is automatically cleared when a short packet is received.
| Value | Description |
|---|---|
| 0 | No automatic packet request |
| 1 | REQPKT will be automatically set when RXPKTRDY bit is cleared. |
Bit 5 – DMAREQENAB DMA Request Enable Control bit
| Value | Description |
|---|---|
| 0 | Disable DMA requests for the RX endpoint. |
| 1 | Enable DMA requests for the RX endpoint. |
Bit 4 – PIDERROR PID Error Status bit
| Value | Description |
|---|---|
| 0 | No error |
| 1 | In ISO transactions, this indicates a PID error in the received packet. |
Bit 3 – DMAREQMODE DMA Request Mode Selection bit
| Value | Description |
|---|---|
| 0 | DMA Request Mode 0 |
| 1 | DMA Request Mode 1 |
Bit 2 – DATATOGGLEWRENABLE Data Toggle Write Enable Control bit
| Value | Description |
|---|---|
| 0 | DATATGGL is not writable |
| 1 | DATATGGL can be written |
Bit 1 – DATATOGGLE Data Toggle bit
When read, this bit indicates the current state of the endpoint data toggle.
If DATATWEN = 1, this bit may be written with the required
setting of the data toggle.
If DATATWEN = 0, any value written to this bit is ignored.
Bit 0 – INCOMPRX Incomplete Packet Status bit
| Value | Description |
|---|---|
| 0 | Written by then software to clear this bit |
| 1 | The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because parts of the data were not received |