29.7.8 Interrupt Flag Status and Clear

Note:

Interrupt flags must be cleared and then read back to confirm the clear before exiting the ISR to avoid double interrupts.
Access to this register is limited to 32-bit width. Byte level access is not allowed.
Reserved bits must always be written as ‘0’.

Table 29-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTFLAG
Offset:	0x14
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	NSCHK
Access	R/W
Reset	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	EXTINT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	EXTINT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – NSCHK Non-secure Check Interrupt Enable

For devices with TrustZone support, the flag is set when write to either NONSEC and NSCHK register and if the related bit of NSCHK is enabled and the related bit of NONSEC is zero. For devices without TrustZone support, this location is reserved.

Value	Description
0	The external interrupt EIC_EXTINTx is disabled.
1	The external interrupt EIC_EXTINTx is enabled.

Bits 15:0 – EXTINT[15:0] External Interrupt

The flag bit x is cleared by writing a '1' to it.

This flag is set when the EIC_EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENCLR.EXTINT[x] or INTENSET.EXTINT[x] is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the External Interrupt x flag.