29.7.11 External Interrupt Sense Configuration

Note:
  1. This register is write protected and can only be written when CTRLA.ENABLE = 0.
  2. Access to this register is limited to 32-bit width. Byte level access is not allowed.
  3. Reserved bits must always be written as ‘0’.
Table 29-13. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Name: CONFIG1
Offset: 0x20
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
 FILTEN15SENSE15[2:0]FILTEN14SENSE14[2:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 FILTEN13SENSE13[2:0]FILTEN12SENSE12[2:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 FILTEN11SENSE11[2:0]FILTEN10SENSE10[2:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 FILTEN9SENSE9[2:0]FILTEN8SENSE8[2:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENx Filter Enable x [x=7..0]

Note:
  1. If corresponding EXTINTx EIC.CONFIGn.SENSEx is set, then EIC.CONFIGn.FILTERx bit must not be set.
ValueDescription
0 Filter is disabled for EIC_EXTINTx pin input.
1 Majority Vote, (best 2 out 3). Filter is enabled for EIC_EXTINTx pin input.

Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense Configuration x [x=7..0]

These bits define on which edge or level the interrupt or event for EIC_EXTINTx pin(s) will be generated.
Note:
  1. If corresponding EXTINTx EIC.CONFIGn.SENSEx is set, then EIC.CONFIGn.FILTERx bit must not be set.
ValueNameDescription
0x0 NONE No detection
0x1 RISE Rising-edge detection
0x2 FALL Falling-edge detection
0x3 BOTH Both-edge detection
0x4 HIGH High-level detection
0x5 LOW Low-level detection
0x6 - 0x7 - Reserved