29.7.6 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Note:
  1. Access to this register is limited to 32-bit width. Byte level access is not allowed.
  2. Reserved bits must always be written as ‘0’.
  3. Interrupt flags must be cleared and then read back to confirm the clear before exiting the ISR to avoid double interrupts.
Table 29-8. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Important: On devices with security attribution Non-Secure accesses, read and write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 NSCHK        
Access R/W 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 EXTINT[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 EXTINT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – NSCHK Non-secure Check Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the NSCHK Interrupt Enable bit. For devices without TrustZone support, this location is reserved.

ValueDescription
0 The external interrupt EIC_EXTINTx is disabled.
1 The external interrupt EIC_EXTINTx is enabled.

Bits 15:0 – EXTINT[15:0] External Interrupt Enable

The bit x of EXTINT enables the interrupt associated with the EIC_EXTINTx pin.

Writing a '0' to bit x has no effect.

Writing a '1' to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt EIC_EXTINTx pin(s).

ValueDescription
0 The external interrupt EIC_EXTINTx is disabled.
1 The external interrupt EIC_EXTINTx is enabled.