29.7.10 External Interrupt Sense Configuration
Note:
- This register is write protected and can only be written when CTRLA.ENABLE = 0.
- Access to this register is limited to 32-bit width. Byte level access is not allowed.
- Reserved bits must always be written as ‘0’.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG0 |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FILTEN7 | SENSE7[2:0] | FILTEN6 | SENSE6[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FILTEN5 | SENSE5[2:0] | FILTEN4 | SENSE4[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FILTEN3 | SENSE3[2:0] | FILTEN2 | SENSE2[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FILTEN1 | SENSE1[2:0] | FILTEN0 | SENSE0[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENx Filter Enable x [x=7..0]
Note:
- If corresponding EXTINTx EIC.CONFIGn.SENSEx is set, then the EIC.CONFIGn.FILTERx bit must not be set.
| Value | Description |
|---|---|
| 0 | Filter is disabled for the EIC_EXTINTx pin input. |
| 1 | Majority Vote (best 2 out 3). Filter is enabled for the EIC_EXTINTx pin input. |
Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense Configuration x [x=7..0]
Note:
- If corresponding EXTINTx EIC.CONFIGn.SENSEx is set, then the EIC.CONFIGn.FILTERx bit must not be set.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No detection |
| 0x1 | RISE | Rising-edge detection |
| 0x2 | FALL | Falling-edge detection |
| 0x3 | BOTH | Both-edge detection |
| 0x4 | HIGH | High-level detection |
| 0x5 | LOW | Low-level detection |
| 0x6 - 0x7 | - | Reserved |