37.12.1 Control B
| Name: | CTRLB |
| Offset: | 0x08 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| L1RESUME | VBUSOK | BUSRESET | SOFE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TSTK | TSTJ | AUTORESUME | SPDCONF[1:0] | RESUME | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 11 – L1RESUME Send USB L1 Resume
Writing 0 to this bit has no effect. 1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation is enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits field also known as BESL (See LPM ECN).See the EXTREG Register.
This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested.
Bit 10 – VBUSOK VBUS is OK
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST is configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is configured and enabled.
| Value | Description |
|---|---|
| 0 | The USB module is notified that the VBUS on the USB line is not powered. |
| 1 | The USB module is notified that the VBUS on the USB line is powered. |
Bit 9 – BUSRESET Send USB Reset
| Value | Description |
|---|---|
| 0 | Reset generation is disabled. It is written to zero when the USB reset is completed or when a device disconnection is detected. Writing zero has no effect. |
| 1 | Generates a USB Reset on the USB bus. |
Bit 8 – SOFE Start-of-Frame Generation Enable
| Value | Description |
|---|---|
| 0 | The SOF generation is disabled and the USB bus is in suspend state. |
| 1 | Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is automatically set at the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume (INTFLAG.DNRSM) or at the end of L1 resume. |
Bit 6 – TSTK Test mode K
| Value | Description |
|---|---|
| 0 | The UTMI transceiver is in normal operation Mode |
| 1 | The UTMI transceiver generates high speed K state for test purposes. |
Bit 5 – TSTJ Test mode J
| Value | Description |
|---|---|
| 0 | The UTMI transceiver is in normal operation Mode |
| 1 | The UTMI transceiver generates high speed J state for test purposes. |
Bit 4 – AUTORESUME Auto Resume Enable
| Value | Description |
|---|---|
| 0 | The Auto Resume is disabled. |
| 1 | Enable Auto Resume |
Bits 3:2 – SPDCONF[1:0] Speed Configuration for Host
These bits select the host speed configuration as shown below
| Value | Description |
|---|---|
| 0x0 | Low, Full and High Speed capable |
| 0x1 | Reserved |
| 0x2 | Reserved |
| 0x3 | Low and Full Speed capable |
Bit 1 – RESUME Send USB Resume
Writing 0 to this bit has no effect. 1: Generates a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.