37.12.7 Host Interrupt Enable Register Set
| Name: | INTENSET |
| Offset: | 0x18 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DDISC | DCONN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RAMACER | UPRSM | DNRSM | WAKEUP | RST | HSOF | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 9 – DDISC Device Disconnection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
| Value | Description |
|---|---|
| 0 | The Device Disconnection interrupt is disabled. |
| 1 | The Device Disconnection interrupt is enabled. |
Bit 8 – DCONN Device Connection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
| Value | Description |
|---|---|
| 0 | The Device Connection interrupt is disabled. |
| 1 | The Device Connection interrupt is enabled. |
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
| Value | Description |
|---|---|
| 0 | The RAM Access interrupt is disabled. |
| 1 | The RAM Access interrupt is enabled. |
Bit 6 – UPRSM Upstream Resume from the device Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
| Value | Description |
|---|---|
| 0 | The Upstream Resume interrupt is disabled. |
| 1 | The Upstream Resume interrupt is enabled. |
Bit 5 – DNRSM Down Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt.
| Value | Description |
|---|---|
| 0 | The Down Resume interrupt is disabled. |
| 1 | The Down Resume interrupt is enabled. |
Bit 4 – WAKEUP Wake Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt request.
| Value | Description |
|---|---|
| 0 | The WakeUp interrupt is disabled. |
| 1 | The WakeUp interrupt is enabled. |
Bit 3 – RST Bus Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Bus Reset interrupt Enable bit and enable the Bus RST interrupt.
| Value | Description |
|---|---|
| 0 | The Bus Reset interrupt is disabled. |
| 1 | The Bus Reset interrupt is enabled. |
Bit 2 – HSOF Host Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Host Start-of-Frame interrupt Enable bit and enable the HSOF interrupt.
| Value | Description |
|---|---|
| 0 | The Host Start-of-Frame interrupt is disabled. |
| 1 | The Host Start-of-Frame interrupt is enabled. |